1. Field of the Invention
The present invention relates generally to image correction technologies and, more particularly, to a method and apparatus for inspecting pattern images for defects, including ultrafine circuit patterns of reticles for use in the manufacture of large-scale integrated (LSI) semiconductor devices and/or low-profile flat panel display devices, such as liquid crystal display (LCD) panels.
2. Description of the Related Art
Usually, LSI chip fabrication comes with cost penalties, so it is inevitable to improve production yields. One of yield reduction factors must be the presence of pattern defects of a reticle used for photolithographically transferring or “imaging” an ultrafine circuit pattern onto semiconductor wafers. In recent years, as LSI chips decrease in feature sizes, pattern defects to be detected decrease in minimum size. This in turn requires a further increase in accuracy of a pattern inspection apparatus for inspecting a reticle for defects.
Currently established pattern defect inspection methodology is generically classified into two approaches, one of which employs die-to-die (DD) comparison techniques, and the other of which uses due-to-database (DB) comparison schemes. The DD comparison is a method for detecting defects through comparison between those images of two square regions or “dies” on a reticle while regarding one of them as an inspection reference pattern image and letting the other be a pattern image under testing. The DB comparison is a method of detecting defects by comparing the sensor data of a die to design data as created from computer-aided design (CAD) data for the LSI design use.
With the quest for further miniaturization of on-reticle circuit patterns, a need is felt to attain the ability to detect extra-fine defects, which are small enough to be buried in a positional offset between picture elements or “pixels” of to-be-compared images, image expansion/shrink, swell, and sensing noises. In the DD or DB comparison also, it becomes very important to accurately perform alignment and image correction in units of sub-pixels, which are typically done prior to the pattern inspection by comparison of the reference pattern image and under-test pattern image.
A known approach to meeting this need is to employ a pre-finishing process prior to execution of the “main” inspection by comparison of a couple of images—i.e., the inspection reference pattern image and the test pattern image. This process includes the steps of performing bicubic interpolation-based alignment in units of subpixels and thereafter sequentially performing image expansion/shrink correction, image swell correction, resize correction, noise averaging processing and others. An example of the image expand/shrink correction is disclosed in JP-A-2000-241136. Unfortunately, mere repeated execution of these corrections would result in occurrence of accumulated errors, which can cause appreciable image degradation or “corruption.” Another problem faced with the prior art lies in difficulties in setting appropriate values for a great number of parameters required for respective corrections and also in setup of an adequate execution order of such correction processes.